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CASES
2005
ACM
13 years 9 months ago
An Esterel processor with full preemption support and its worst case reaction time analysis
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...
LCPC
2004
Springer
14 years 25 days ago
Supporting SQL-3 Aggregations on Grid-Based Data Repositories
There is an increasing trends towards distributed and shared repositories for storing scientific datasets. Developing applications that retrieve and process data from such reposit...
Li Weng, Gagan Agrawal, Ümit V. Çataly...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
13 years 11 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
VLSID
1999
IEEE
99views VLSI» more  VLSID 1999»
13 years 11 months ago
Array Index Allocation under Register Constraints in DSP Programs
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
Anupam Basu, Rainer Leupers, Peter Marwedel
HIPC
2000
Springer
13 years 11 months ago
Instruction Level Distributed Processing
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
James E. Smith