This paper addresses the question of producing modular sequential imperative code from synchronous data-flow networks. Precisely, given a system with several input and output flow...
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
—Default ARTMAP combines winner-take-all category node activation during training, distributed activation during testing, and a set of default parameter values that define a read...
Because of cost and resource constraints, sensor nodes do not have a complicated hardware architecture or operating system to protect program safety. Hence, the notorious buffer-o...
— In this paper, we consider a 2-hop wireless diversity relay network. We explore transmit power allocation among the source and relays to maximize the received signal to noise r...