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DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 11 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
CCGRID
2010
IEEE
13 years 8 months ago
Energy Efficient Resource Management in Virtualized Cloud Data Centers
Rapid growth of the demand for computational power by scientific, business and web-applications has led to the creation of large-scale data centers consuming enormous amounts of el...
Anton Beloglazov, Rajkumar Buyya
AIMS
2008
Springer
13 years 9 months ago
Entwined Influences of Users' Behaviour and QoS: A Multi-model Approach
In distributed, dynamic networks and applications, such as Peer-to-Peer (P2P), users'behaviour and quality of service/quality of experiment1 are known to influence each other....
Julien Siebert, Vincent Chevrier, Laurent Ciarlett...
TC
2008
13 years 7 months ago
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
Assaf Shacham, Keren Bergman, Luca P. Carloni
BMCBI
2010
118views more  BMCBI 2010»
13 years 7 months ago
Identifying differentially regulated subnetworks from phosphoproteomic data
Background: Various high throughput methods are available for detecting regulations at the level of transcription, translation or posttranslation (e.g. phosphorylation). Integrati...
Martin Klammer, Klaus Godl, Andreas Tebbe, Christo...