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2005
IEEE
110views Hardware» more  DATE 2005»
14 years 1 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
24
Voted
PTS
2000
108views Hardware» more  PTS 2000»
13 years 9 months ago
Determination of Test Configurations for Pair-Wise Interaction Coverage
Systems constructed from components, including distributed systems, consist of a number of elements that interact with each other. As the number of network elements or interchangea...
Alan W. Williams
ACCESSNETS
2008
Springer
14 years 2 months ago
Loop Identification and Capacity Estimation of Digital Subscriber Lines with Single Ended Line Testing
Digital subscriber lines offer the possibility to deliver broadband services over the existing telephone network. Still, beforehand subscriber loops must be tested to see whether t...
Carine Neus, Wim Foubert, Leo Van Biesen
KIVS
1997
Springer
13 years 12 months ago
Conformance Testing of Objects in Distributed Processing Systems
The object model is a very popular paradigm for building distributed applications. Several standardisation efforts are underway that define architectures for distributed computing...
Brigitte Bär, Kurt Geihs
APSEC
2006
IEEE
14 years 1 months ago
Testing of Timer Function Blocks in FBD
Testing for time-related behaviors of PLC software is important and should be performed carefully. We propose a structural testing technique on Function Block Diagram(FBD) network...
Eunkyoung Jee, Seungjae Jeon, Hojung Bang, Sung De...