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MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
15 years 9 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
137
Voted
RTAS
2006
IEEE
15 years 9 months ago
Network-Code Machine: Programmable Real-Time Communication Schedules
Distributed hard real-time systems require guaranteed communication. One common approach is to restrict network access by enforcing a time-division multiple access (TDMA) schedule...
Sebastian Fischmeister, Oleg Sokolsky, Insup Lee
DSN
2005
IEEE
15 years 9 months ago
Reversible Fault-Tolerant Logic
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
P. Oscar Boykin, Vwani P. Roychowdhury
280
Voted
HYBRID
2011
Springer
14 years 3 months ago
Resource constrained LQR control under fast sampling
We investigate a state feedback Linear Quadratic Regulation problem with a constraint on the number of actuation signals that can be updated simultaneously. Such a constraint aris...
Jerome Le Ny, Eric Feron, George J. Pappas
165
Voted
NOCS
2008
IEEE
15 years 10 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...