49 search results - page 3 / 10 » Neural Compiler Technology for a Parallel Architecture |
PPOPP
2009
ACM
14 years 9 months ago
2009
ACM
The efficient mapping of program parallelism to multi-core processors is highly dependent on the underlying architecture. This paper proposes a portable and automatic compiler-bas...
ASPLOS
1998
ACM
14 years 25 days ago
1998
ACM
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
ICPP
2007
IEEE
14 years 2 months ago
2007
IEEE
As multi-core microprocessors are becoming widely adopted, the need to extract thread-level parallelism (TLP) from single-threaded applications in a seamless fashion increases. In...
DELTA
2010
IEEE
14 years 1 months ago
2010
IEEE
High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
APCSAC
2000
IEEE
14 years 6 days ago
2000
IEEE
Dataflow computation models enable simpler and more efficient management of the memory hierarchy - a key barrier to the performance of many parallel programs. This paper describes...