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ISCAS
2006
IEEE
133views Hardware» more  ISCAS 2006»
14 years 1 months ago
Neuronal ion-channel dynamics in silicon
Abstract— We present a simple silicon circuit for modelling voltagedependent ion channels found within neural cells, capturing both the gating particle’s sigmoidal activation (...
Kai M. Hynna, Kwabena Boahen
ICC
2007
IEEE
114views Communications» more  ICC 2007»
14 years 2 months ago
An FPGA Implementation of Dirty Paper Precoder
—Dirty paper code (DPC) can be used in a number of communication network applications; broadcast channels, multiuser interference channels and ISI channels to name a few. We stud...
Pankaj Bhagawat, Weihuang Wang, Momin Uppal, Gwan ...
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 5 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
HYBRID
2011
Springer
12 years 7 months ago
Resource constrained LQR control under fast sampling
We investigate a state feedback Linear Quadratic Regulation problem with a constraint on the number of actuation signals that can be updated simultaneously. Such a constraint aris...
Jerome Le Ny, Eric Feron, George J. Pappas
SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
14 years 2 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...