947 search results - page 102 / 190 » New Delay Analysis in High Speed Networks |
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
AINA
2009
IEEE
14 years 1 months ago
2009
IEEE
Keeping router buffering low helps minimise delay (as well as keeping router costs low), whilst increasing buffering minimises loss. This is a trade-off for which there is no sing...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
RTAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Over the last thirty years, the MIL-STD 1553B data bus has been used in many embedded systems, like aircrafts, ships, missiles and satellites. However, the increasing number and c...
EUROISI
2008
13 years 9 months ago
2008
The tragic events of September 11th have caused drastic effects on many aspects of society. Academics in the fields of computational and information science have been called upon ...