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FPGA
2010
ACM
181views FPGA» more  FPGA 2010»
13 years 11 months ago
Efficient multi-ported memories for FPGAs
Multi-ported memories are challenging to implement with FPGAs since the provided block RAMs typically have only two ports. We present a thorough exploration of the design space of...
Charles Eric LaForest, J. Gregory Steffan
FPL
2005
Springer
140views Hardware» more  FPL 2005»
14 years 1 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
ICC
2007
IEEE
137views Communications» more  ICC 2007»
14 years 2 months ago
A Novel Algorithm and Architecture for High Speed Pattern Matching in Resource-Limited Silicon Solution
— Network Intrusion Detection Systems (NIDS) are more and more important for identifying and preventing the malicious attacks over the network. This paper proposes a novel cost-e...
Nen-Fu Huang, Yen-Ming Chu, Chi-Hung Tsai, Chen-Yi...
INFOCOM
2010
IEEE
13 years 5 months ago
FlashTrie: Hash-based Prefix-Compressed Trie for IP Route Lookup Beyond 100Gbps
It is becoming apparent that the next generation IP route lookup architecture needs to achieve speeds of 100Gbps and beyond while supporting both IPv4 and IPv6 with fast real-time ...
Masanori Bando, H. Jonathan Chao
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 7 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek