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ISCA
2008
IEEE
112views Hardware» more  ISCA 2008»
14 years 2 months ago
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
Onur Mutlu, Thomas Moscibroda
TVLSI
2008
164views more  TVLSI 2008»
13 years 7 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
LCN
2002
IEEE
14 years 15 days ago
A New Location Management Strategy Based on User Mobility Pattern for Wireless Networks
For a wireless network to effectively deliver services to the mobile users, it must have an efficient way to track them. The location management fulfills this task through locat...
Wenchao Ma, Yuguang Fang
SIGSOFT
1998
ACM
13 years 11 months ago
Effective Whole-Program Analysis in the Presence of Pointers
Understanding large software systems is difficult. Traditionally, automated tools are used to assist program understanding. However, the representations constructed by these tool...
Darren C. Atkinson, William G. Griswold
ISSRE
2006
IEEE
14 years 1 months ago
Memoized Forward Computation of Dynamic Slices
Forward computation of dynamic slices is necessary to support interactive debugging and online analysis of long running programs. However, the overhead of existing forward computi...
Wes Masri, Nagi Nahas, Andy Podgurski