621 search results - page 26 / 125 » Next Generation Network Processors |
ICC
2009
IEEE
13 years 6 months ago
2009
IEEE
In this paper, an efficient design for implementing binary sequence generator on 32-bit instruction execution mode TI TMS320C6416 DSP is presented. The main goal is to achieve high...
MCU
2007
13 years 10 months ago
2007
We discuss the power of networks of evolutionary processors where only two types of nodes are allowed. We prove that (up to an intersection with a monoid) every recursively enumer...
ISCA
1996
IEEE
14 years 23 days ago
1996
IEEE
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
GECCO
2003
Springer
14 years 1 months ago
2003
Springer
Abstract. A hybrid network of evolutionary processors consists of several processors which are placed in nodes of a virtual graph and can perform one simple operation only on the w...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and ...