152 search results - page 5 / 31 » Noise considerations in circuit optimization |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
The existing decoupling capacitance optimization approaches meet constraints on input impedance for package. In this paper, we show that using impedance as constraints leads to la...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
The effect of shield structures for local wirings of analog integrated circuits on crosstalk is determined by electromagnetic simulation. The crosstalk of parallel wirings is redu...