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VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 11 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
CHES
2006
Springer
88views Cryptology» more  CHES 2006»
13 years 11 months ago
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA). Since then, several methods, such as Wave Dynamic Differential Lo...
Zhimin Chen, Yujie Zhou
GECCO
2006
Springer
202views Optimization» more  GECCO 2006»
13 years 11 months ago
Inference of genetic networks using S-system: information criteria for model selection
In this paper we present an evolutionary approach for inferring the structure and dynamics in gene circuits from observed expression kinetics. For representing the regulatory inte...
Nasimul Noman, Hitoshi Iba
CHI
2005
ACM
13 years 9 months ago
A closed-loop tactor frequency control system for vibrotactile feedback
In this paper, we address the problem of maintaining a precise frequency in vibrating motors for use as vibrotactile cueing devices. Our solution utilizes a piezoelectric film sen...
Justin Cohen, Masataka Niwa, Robert W. Lindeman, H...
ACSD
2010
IEEE
219views Hardware» more  ACSD 2010»
13 years 5 months ago
The Model Checking View to Clock Gating and Operand Isolation
Abstract--Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step pr...
Jens Brandt, Klaus Schneider, Sumit Ahuja, Sandeep...