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TVLSI
2008
111views more  TVLSI 2008»
13 years 7 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
CAV
2008
Springer
105views Hardware» more  CAV 2008»
13 years 9 months ago
THOR: A Tool for Reasoning about Shape and Arithmetic
We describe Thor (Tool for Heap-Oriented Reasoning), a tool based on separation logic that is capable of reasoning automatically about heap-manipulating programs. There are several...
Stephen Magill, Ming-Hsien Tsai, Peter Lee, Yih-Ku...
DAC
1997
ACM
13 years 11 months ago
Static Timing Analysis of Embedded Software
This paper examines the problem of statically analyzing the performance of embedded software. This problem is motivated by the increasing growth of embedded systems and a lack of ...
Sharad Malik, Margaret Martonosi, Yau-Tsun Steven ...
AIEDU
2007
108views more  AIEDU 2007»
13 years 7 months ago
Explicit Reflection in Prolog-Tutor
This paper describes a reflection-based approach for open learner modeling (OLM). Tutoring dialogues are used by learners to explicitly reveal their own knowledge state to themselv...
Joséphine M. P. Tchétagni, Roger Nka...
BMCBI
2008
153views more  BMCBI 2008»
13 years 7 months ago
Version VI of the ESTree db: an improved tool for peach transcriptome analysis
Background: The ESTree database (db) is a collection of Prunus persica and Prunus dulcis EST sequences that in its current version encompasses 75,404 sequences from 3 almond and 1...
Barbara Lazzari, Andrea Caprera, Alberto Vecchiett...