A technique for transformation of definite logic programs is presented. A first phase performs an analysis of the extended call/exit patterns of the source program. It is shown tha...
fects are statically generated program abstractions, that can be model checked for verification of assertions in a temporal program logic. In this paper we develop a type and eff...
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
We present an analysis which takes as its input a sequential program, augmented with annotations indicating potential parallelization opportunities, and a sequential proof, writte...