Sciweavers

521 search results - page 27 / 105
» Non-linear image processing in hardware
Sort
View
AHS
2006
IEEE
93views Hardware» more  AHS 2006»
14 years 1 months ago
An FPGA Implemented Processor Architecture with Adaptive Resolution
Reconfigurable software has been applied for a long time. Reconfigurable technology also provides possibility for reconfiguring hardware but this has not been much exploited so...
Jim Torresen, Jonas Jakobsen
IROS
2009
IEEE
191views Robotics» more  IROS 2009»
14 years 2 months ago
Development of high-speed and real-time vision platform, H3 vision
— In this paper, we introduce a high-speed vision platform, H3 (Hiroshima Hyper Human) Vision, which can simultaneously process a 1024× 1024 pixel image at 1000 fps and a 256× ...
Idaku Ishii, Taku Taniguchi, Ryo Sukenobe, Kenichi...
TEI
2009
ACM
95views Hardware» more  TEI 2009»
14 years 2 months ago
Shoebox: mixing storage and display of digital images in the home
This paper describes the rationale and design process for Shoebox, a “digital box” that combines the storage and display of digital images in the home in one unit. By combinin...
Richard Banks, Abigail Sellen
ICCAD
2007
IEEE
123views Hardware» more  ICCAD 2007»
14 years 4 months ago
Mapping model with inter-array memory sharing for multidimensional signal processing
Abstract – The storage requirements in data-intensive signal processing systems (including applications in video and image processing, artificial vision, medical imaging, real-t...
Ilie I. Luican, Hongwei Zhu, Florin Balasa
DELTA
2008
IEEE
14 years 1 months ago
A Visual Notation for Processor and Resource Scheduling
Scheduling of concurrent processors in a real-time image processing system on FPGA (Field programmable gate array) hardware is a not a trivial task. We propose a number of graphic...
Christopher T. Johnston, Paul J. Lyons, Donald G. ...