325 search results - page 4 / 65 » Non-uniform Instruction Scheduling |
ML
2002
ACM
13 years 7 months ago
2002
ACM
The execution order of a block of computer instructions on a pipelined machine can make a difference in running time by a factor of two or more. Compilers use heuristic schedulers...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
As the number of cores per machine increases, memory architectures are being redesigned to avoid bus contention and sustain higher throughput needs. The emergence of Non-Uniform M...
TC
1998
13 years 7 months ago
1998
—We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with ...
CP
2008
Springer
13 years 9 months ago
2008
Springer
Modern computer architectures have complex features that can only be fully taken advantage of if the compiler schedules the compiled code. A standard region of code for scheduling ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...