94 search results - page 8 / 19 » Novel CNTFET-based Reconfigurable Logic Gate Design |
TVLSI
2008
13 years 8 months ago
2008
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
IJVR
2007
13 years 8 months ago
2007
—To construct 3D virtual scenes from two-dimensional images with depth information, image warping techniques could be used. In this paper, a novel approach of cylindrical depth i...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...