138 search results - page 5 / 28 » Novel architecture for loop acceleration: a case study |
CGO
2009
IEEE
14 years 4 months ago
2009
IEEE
Compilers employ many aggressive code transformations to achieve highly optimized code. However, because of complex target architectures and unpredictable optimization interaction...
FCCM
2011
IEEE
13 years 1 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
VLSISP
2008
13 years 9 months ago
2008
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
ICS
2009
Tsinghua U.
14 years 4 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...