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TVLSI
2008
108views more  TVLSI 2008»
13 years 9 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
FPL
2007
Springer
190views Hardware» more  FPL 2007»
14 years 3 months ago
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems
Today’s heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of thes...
Andreas Herrholz, Frank Oppenheimer, Philipp A. Ha...
LCN
2002
IEEE
14 years 2 months ago
Design and Analysis of a Dynamically Reconfigurable Network Processor
The combination of high-performance processing power and flexibility found in network processors (NPs) has made them a good solution for today’s packet processing needs. Similar...
Ian A. Troxel, Alan D. George, Sarp Oral
BIRTHDAY
2008
Springer
13 years 11 months ago
Graph-Based Design and Analysis of Dynamic Software Architectures
We illustrate two ways to address the specification, modelling and analysis of dynamic software architectures using: i) ordinary typed graph transformation techniques implemented i...
Roberto Bruni, Antonio Bucchiarone, Stefania Gnesi...
ESANN
2006
13 years 10 months ago
Visual nonlinear discriminant analysis for classifier design
Abstract. We present a new method for analyzing classifiers by visualization, which we call visual nonlinear discriminant analysis. Classifiers that output posterior probabilities ...
Tomoharu Iwata, Kazumi Saito, Naonori Ueda