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ISVLSI
2003
IEEE
91views VLSI» more  ISVLSI 2003»
14 years 2 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
Shamik Das, Anantha Chandrakasan, Rafael Reif
CHI
1999
ACM
14 years 1 months ago
The Design and Evaluation of a High-Performance Soft Keyboard
The design and evaluation of a high performance soft keyboard for mobile systems are described. Using a model to predict the upper-bound text entry rate for soft keyboards, we des...
I. Scott MacKenzie, Shawn X. Zhang
ICC
2007
IEEE
140views Communications» more  ICC 2007»
14 years 3 months ago
Performance Analysis of Full-rate STBCs from Coordinate Interleaved Orthogonal Designs
— In this paper, we derive the theoretical symbol error rate (SER) for a full-rate space-time block coded (STBCed) system with coordinate interleaved orthogonal designs (CIODs) o...
Ying Rao Wei, M. Z. Wang
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
14 years 2 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
DAC
2000
ACM
14 years 10 months ago
Multiple Si layer ICs: motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...