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ISPASS
2007
IEEE
14 years 3 months ago
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhan...
SASN
2003
ACM
14 years 2 months ago
Admission control in Peer-to-Peer: design and performance evaluation
Peer-to-Peer (P2P) applications and services are very common in today’s computing. The popularity of the P2P paradigm prompts the need for specialized security services which ma...
Nitesh Saxena, Gene Tsudik, Jeong Hyun Yi
GLOBECOM
2009
IEEE
14 years 3 months ago
Robust Cooperative Relaying in a Wireless LAN: Cross-Layer Design and Performance Analysis
—A key technology in cooperative communications is distributed space-time coding (DSTC) which achieves spatial diversity gain from multiple relays. A novel DSTC, called randomize...
Pei Liu, Chun Nie, Elza Erkip, Shivendra S. Panwar
HIPC
2005
Springer
14 years 2 months ago
XCAT-C++: Design and Performance of a Distributed CCA Framework
In this paper we describe the design and implementation of a C++ based Common Component Architecture (CCA) framework, XCAT-C++. It can efficiently marshal and unmarshal large data...
Madhusudhan Govindaraju, Michael R. Head, Kenneth ...
ARITH
2003
IEEE
14 years 2 months ago
High-Performance Left-to-Right Array Multiplier Design
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
Zhijun Huang, Milos D. Ercegovac