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» On Bus Graph Realizability
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ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
DFT
2000
IEEE
106views VLSI» more  DFT 2000»
13 years 11 months ago
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications
We present a configuration technique for a Large Area Integrated Circuit (LAIC) which is manufactured by wafer stepping. A LAIC consists of four identical subsystems, i.e., a subs...
Markus Rudack, Michael Redeker, Dieter Treytnar, O...
CORR
2010
Springer
58views Education» more  CORR 2010»
13 years 6 months ago
Realizable Paths and the NL vs L Problem
A celebrated theorem of Savitch [Sav70] states that NSPACE(S) ⊆ DSPACE(S2 ). In particular, Savitch gave a deterministic algorithm to solve ST-CONNECTIVITY (an NL-complete probl...
Shiva Kintali
DM
2008
76views more  DM 2008»
13 years 7 months ago
Graphic sequences with a realization containing a complete multipartite subgraph
A nonincreasing sequence of nonnegative integers = (d1, d2, ..., dn) is graphic if there is a (simple) graph G of order n having degree sequence . In this case, G is said to reali...
Guantao Chen, Michael Ferrara, Ronald J. Gould, Jo...
SAC
2008
ACM
13 years 6 months ago
Collaborative software engineering on large-scale models: requirements and experience in ModelBus
This work presents an approach for realizing Model-Driven software engineering in the distributed and multi-developers context. It particularly focuses on the scalability problems...
Prawee Sriplakich, Xavier Blanc, Marie-Pierre Gerv...