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» On Bus Graph Realizability
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DAC
1996
ACM
13 years 11 months ago
Electromigration Reliability Enhancement via Bus Activity Distribution
: Electromigration induced degradation in integrated circuits has been accelerated by continuous scaling of device dimensions. We present a methodology for synthesizing high-reliab...
Aurobindo Dasgupta, Ramesh Karri
HOTI
2008
IEEE
14 years 1 months ago
A High-Speed Optical Multi-Drop Bus for Computer Interconnections
Buses have historically provided a flexible communications structure in computer systems. However, signal integrity constraints of high-speed electronics have made multi-drop elec...
Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, ...
TVLSI
2008
164views more  TVLSI 2008»
13 years 7 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
INFOCOM
2011
IEEE
12 years 11 months ago
Timely data delivery in a realistic bus network
Abstract—WiFi-enabled buses and stops may form the backbone of a metropolitan delay tolerant network, that exploits nearby communications, temporary storage at stops, and predict...
Utku Acer, Paolo Giaccone, David Hay, Giovanni Neg...
COMBINATORICS
2006
100views more  COMBINATORICS 2006»
13 years 7 months ago
Parity Versions of 2-Connectedness
This paper introduces parity versions of familiar graph theoretic results, in particular results related to 2-connectedness. The even and odd circuit connected graphs are characte...
C. Little, A. Vince