216 search results - page 17 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
ICPADS
1994
IEEE
13 years 12 months ago
1994
IEEE
: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence sc...
SIGCSE
1999
ACM
14 years 2 days ago
1999
ACM
The wide-spread use of microprocessor based systems that utilize cache memory to alleviate excessively long DRAM access times introduces a new dimension in the quest to obtain goo...
HPCA
1997
IEEE
13 years 12 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...