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SAMOS
2007
Springer
14 years 1 months ago
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
Nainesh Agarwal, Nikitas J. Dimopoulos
IPPS
2006
IEEE
14 years 1 months ago
Parallel implementation of the replica exchange molecular dynamics algorithm on Blue Gene/L
The Replica Exchange method is a popular approach for studying the folding thermodynamics of small to modest size proteins in explicit solvent, since it is easily parallelized. Ho...
Maria Eleftheriou, Aleksandr Rayshubskiy, Jed W. P...
MICRO
2006
IEEE
102views Hardware» more  MICRO 2006»
14 years 1 months ago
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multi...
Sangyeun Cho, Lei Jin
ACMMSP
2006
ACM
247views Hardware» more  ACMMSP 2006»
14 years 1 months ago
A flexible data to L2 cache mapping approach for future multicore processors
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
Lei Jin, Hyunjin Lee, Sangyeun Cho
EUROPAR
2003
Springer
14 years 21 days ago
Obtaining Hardware Performance Metrics for the BlueGene/L Supercomputer
Hardware performance monitoring is the basis of modern performance analysis tools for application optimization. We are interested in providing such performance analysis tools for t...
Pedro Mindlin, José R. Brunheroto, Luiz De ...