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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 7 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
14 years 7 months ago
Post-placement voltage island generation
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C...
ICCAD
2006
IEEE
149views Hardware» more  ICCAD 2006»
14 years 7 months ago
Thermal sensor allocation and placement for reconfigurable systems
Temperature monitoring using thermal sensors is an essential tool for evaluating the thermal behavior and sustaining the reliable operation in high-performance and high-power syst...
Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci...
ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
14 years 7 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 7 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
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