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» On Local Register Allocation
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ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
14 years 2 months ago
RENO - A Rename-Based Instruction Optimizer
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
Vlad Petric, Tingting Sha, Amir Roth
ACMMSP
2005
ACM
129views Hardware» more  ACMMSP 2005»
14 years 2 months ago
A locality-improving dynamic memory allocator
In general-purpose applications, most data is dynamically allocated. The memory manager therefore plays a crucial role in application performance by determining the spatial locali...
Yi Feng, Emery D. Berger
LCTRTS
2009
Springer
14 years 3 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
IEEEPACT
2005
IEEE
14 years 2 months ago
Memory Coloring: A Compiler Approach for Scratchpad Memory Management
Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in perfor...
Lian Li 0002, Lin Gao 0002, Jingling Xue
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
14 years 1 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith