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    DATE
    2008
    IEEE
    76views Hardware» more  DATE 2008»
    On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits
    16 years 1 months ago
    On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits
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    Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu
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    186
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    VTS
    1996
    IEEE
    112views Hardware» more  VTS 1996»
    Optimal voltage testing for physically-based faults
    15 years 11 months ago
    Optimal voltage testing for physically-based faults
    Download  faculty.cs.tamu.edu
    In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
    Yuyun Liao, D. M. H. Walker
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