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On Modeling and Testing of Lithography Related Open Faults i...
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On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits
15 years 10 months ago
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Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu
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1996
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Optimal voltage testing for physically-based faults
15 years 8 months ago
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In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
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