Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
Michael A. Kochte, Marcel Schaal, Hans-Joachim Wun...
As the size of parallel computers increases, as well as the number of sources per router node, congestion inside the interconnection network rises significantly. In such systems, ...
Parallel functional programs with implicit communication often generate purely hierarchical communication topologies during execution: communication only happens between parent an...
In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to cache banks in a round-...
Alberto Ros, Marcelo Cintra, Manuel E. Acacio, Jos...
We study Reader-Writer Exclusion [1], a well-known variant of the Mutual Exclusion problem [2] where processes are divided into two classes–readers and writers–and multiple re...