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» On Predictability of Caches for Real-Time Applications
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ASAP
2002
IEEE
85views Hardware» more  ASAP 2002»
14 years 19 days ago
Predictable Instruction Caching for Media Processors
The determinism of instruction cache performance can be considered a major problem in multi-media devices which hope to maximise their quality of service. If instructions are evic...
James Irwin, David May, Henk L. Muller, Dan Page
ICS
1995
Tsinghua U.
13 years 11 months ago
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
Antonio González, Carlos Aliagas, Mateo Val...
RTCSA
2007
IEEE
14 years 1 months ago
A NOR Emulation Strategy over NAND Flash Memory
This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobi...
Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-...
CSREAESA
2003
13 years 9 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
14 years 28 days ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...