The determinism of instruction cache performance can be considered a major problem in multi-media devices which hope to maximise their quality of service. If instructions are evic...
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobi...
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...