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» On Reconfigurable Co-processing Units
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ECAI
2008
Springer
13 years 9 months ago
Intelligent adaptive monitoring for cardiac surveillance
Monitoring patients in intensive care units is a critical task. Simple condition detection is generally insufficient to diagnose a patient and may generate many false alarms to the...
Lucie Callens, Guy Carrault, Marie-Odile Cordier, ...
PPL
2008
144views more  PPL 2008»
13 years 7 months ago
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronizati...
Konstantinos Tatas, Costas Kyriacou, Paraskevas Ev...
SPAA
2009
ACM
14 years 8 months ago
Buffer management for colored packets with deadlines
We consider buffer management of unit packets with deadlines for a multi-port device with reconfiguration overhead. The goal is to maximize the throughput of the device, i.e., the...
Yossi Azar, Uriel Feige, Iftah Gamzu, Thomas Mosci...
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
13 years 11 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
14 years 2 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha