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ISCA
2005
IEEE
90views Hardware» more  ISCA 2005»
14 years 1 months ago
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...
SAS
2007
Springer
126views Formal Methods» more  SAS 2007»
14 years 1 months ago
Hierarchical Pointer Analysis for Distributed Programs
We present a new pointer analysis for use in shared memory programs running on hierarchical parallel machines. The analysis is motivated by the partitioned global address space lan...
Amir Kamil, Katherine A. Yelick
SIGARCH
2008
96views more  SIGARCH 2008»
13 years 7 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
ASPLOS
2000
ACM
13 years 12 months ago
Hoard: A Scalable Memory Allocator for Multithreaded Applications
Parallel, multithreaded C and C++ programs such as web servers, database managers, news servers, and scientific applications are becoming increasingly prevalent. For these applic...
Emery D. Berger, Kathryn S. McKinley, Robert D. Bl...
ICS
1999
Tsinghua U.
13 years 11 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer