Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
Increasing power densities and the high cost of low thermal resistance packages and cooling solutions make it impractical to design processors for worst-case temperature scenarios...
Thidapat Chantem, Xiaobo Sharon Hu, Robert P. Dick
We present a storage management framework for Web 2.0 services that places users back in control of their data. Current Web services complicate data management due to data lock-in...
Neal H. Walfield, Paul T. Stanton, John Linwood Gr...
Abstract. To ensure the consistency of database subsystems involved in communication systems (e.g., telephone systems), appropriate scheduled maintenance policies are necessary. Au...
Stefano Porcarelli, Felicita Di Giandomenico, Amin...
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...