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» On Some Systems Controlled by the Structure of Their Memory
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ASPLOS
2010
ACM
13 years 12 months ago
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the memory subsystem. If resource sharing is unfair, some applications can be delayed significantl...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 11 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
COMAD
2008
13 years 10 months ago
Concurrency Control in Distributed MRA Index Structure
Answering aggregate queries like sum, count, min, max over regions containing moving objects is often needed for virtual world applications, real-time monitoring systems, etc. Sin...
Neha Singh, S. Sudarshan
ICDE
1999
IEEE
91views Database» more  ICDE 1999»
14 years 10 months ago
Real-Time Data Access Control on B-Tree Index Structures
This paper proposes methodologies to control the access of B-tree-indexed data in a batch and real-time fashion. Algorithms are proposed to insert, query, delete, and rebalance B-...
Tei-Wei Kuo, Chih-Hung Wei, Kam-yiu Lam
GECCO
2006
Springer
185views Optimization» more  GECCO 2006»
14 years 8 days ago
Memory analysis and significance test for agent behaviours
Many agent problems in a grid world have a restricted sensory information and motor actions. The environmental conditions need dynamic processing of internal memory. In this paper...
DaeEun Kim