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» On Structural vs. Functional Testing for Delay Faults
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ETS
2011
IEEE
212views Hardware» more  ETS 2011»
12 years 7 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...
VTS
2000
IEEE
95views Hardware» more  VTS 2000»
14 years 2 hour ago
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
Li Chen, Sujit Dey
ISORC
2006
IEEE
14 years 1 months ago
Diagnostic Framework for Integrated Time-Triggered Architectures
Integrated architectures promise substantial technical and economic benefits in the development of distributed embedded real-time systems. In the context of diagnosis new diagnos...
Philipp Peti, Roman Obermaisser
ISESE
2006
IEEE
14 years 1 months ago
An industrial case study of structural testing applied to safety-critical embedded software
Effective testing of safety-critical real-time embedded software is difficult and expensive. Many companies are hesitant about the cost of formalized criteria-based testing and a...
Jing Guan, Jeff Offutt, Paul Ammann
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
13 years 12 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar