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DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 10 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
15 years 10 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
SIAMCOMP
2010
172views more  SIAMCOMP 2010»
14 years 11 months ago
Deterministic Polynomial Time Algorithms for Matrix Completion Problems
We present new deterministic algorithms for several cases of the maximum rank matrix completion problem (for short matrix completion), i.e. the problem of assigning values to the ...
Gábor Ivanyos, Marek Karpinski, Nitin Saxen...
INFOCOM
2010
IEEE
15 years 2 months ago
CapAuth: A Capability-based Handover Scheme
—Existing handover schemes in wireless LANs, 3G/4G networks, and femtocells rely upon protocols involving centralized authentication servers and one or more access points. These ...
Liang Cai, Sridhar Machiraju, Hao Chen
TC
2008
15 years 4 months ago
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
On-chip networks (OCNs) have been proposed to solve the increasing scale and complexity of the designs in nanoscale multicore VLSI designs. The concept of irregular meshes is an im...
Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Ken...