774 search results - page 151 / 155 » On Timed Alternating Simulation for Concurrent Timed Games |
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
ADHOCNOW
2006
Springer
14 years 1 months ago
2006
Springer
Flash memory is often the technology of choice for sensor networks because of its cost-effectiveness and attractive energy properties. In storage-constrained sensor network applica...
MICRO
2005
IEEE
14 years 29 days ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
TRIDENTCOM
2005
IEEE
14 years 29 days ago
2005
IEEE
Today’s Internet backbone networking devices need to be tested under realistic traffic conditions at transmission rates of OC-48 and above. While commercially available synthet...
CLADE
2003
IEEE
14 years 21 days ago
2003
IEEE
With rapid technological advances in network infrastructure, programming languages, compatible component interfaces and so many more areas, today the computational Grid has evolve...