1529 search results - page 105 / 306 » On Timing Analysis of Combinational Circuits |
TACAS
2010
Springer
14 years 3 months ago
2010
Springer
Boolean satisfiability (SAT) and its extensions are becoming a core technology for the analysis of systems. The SAT-based approach divides into three steps: encoding, preprocessin...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
CASES
2010
ACM
13 years 5 months ago
2010
ACM
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...
GLOBECOM
2006
IEEE
14 years 2 months ago
2006
IEEE
— High-rate space-time-frequency block codes (STFBC) are promising for achieving high bandwidth efficiency, low overhead and latency. Recently, a class of low-complexity STFBC m...
ICISC
2007
13 years 9 months ago
2007
Abstract. We investigate three side channel attacks on ABSG, a variant of irregularly decimated generators (IDG). The three attacks are timing analysis, phase-shift fault analysis ...