Boolean satisfiability (SAT) and its extensions are becoming a core technology for the analysis of systems. The SAT-based approach divides into three steps: encoding, preprocessin...
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
David Bol, Dina Kamel, Denis Flandre, Jean-Didier ...
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...
Ted Huffmire, Timothy E. Levin, Michael Bilzor, Cy...
— High-rate space-time-frequency block codes (STFBC) are promising for achieving high bandwidth efficiency, low overhead and latency. Recently, a class of low-complexity STFBC m...
Abstract. We investigate three side channel attacks on ABSG, a variant of irregularly decimated generators (IDG). The three attacks are timing analysis, phase-shift fault analysis ...