1529 search results - page 149 / 306 » On Timing Analysis of Combinational Circuits |
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
ASPDAC
2006
ACM
13 years 12 months ago
2006
ACM
Due to false paths and multi-cycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing a...
CHES
2006
Springer
13 years 12 months ago
2006
Springer
This article starts with a discussion of three different attacks on masked AES hardware implementations. This discussion leads to the conclusion that glitches in masked circuits po...
IJVR
2006
13 years 8 months ago
2006
In this paper, we will present an overview of existing research in the vast area of IVH systems. We will also present our ongoing work on improving the expressive capabilities of I...
INFOCOM
2010
IEEE
13 years 6 months ago
2010
IEEE
We investigate the fundamental capacity limits of space-time journeys of information in mobile and Delay Tolerant Networks (DTNs), where information is either transmitted or carrie...