1529 search results - page 170 / 306 » On Timing Analysis of Combinational Circuits |
FMCAD
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. This paper presents a scalable method for parallel symbolic on-the-fly model checking in a distributed memory environment. Our method combines a scheme for on-the-fly mod...
TCAD
2002
13 years 7 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
ICPADS
2007
IEEE
14 years 2 months ago
2007
IEEE
We consider a system with a dispatcher and several identical servers in parallel. Task processing times are known upon arrival. We first study the impact of the local scheduling ...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...
TIME
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— We present a specification language and algorithms for the online and offline monitoring of synchronous systems including circuits and embedded systems. Such monitori...