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» On Timing Analysis of Combinational Circuits
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IPPS
1998
IEEE
14 years 5 days ago
A Comparative Study of Five Parallel Genetic Algorithms Using the Traveling Salesman Problem
Parallel genetic algorithms (PGAs) have been developed to reduce the large execution times that are associated with serial genetic algorithms (SGAs). They have also been used to s...
Lee Wang, Anthony A. Maciejewski, Howard Jay Siege...
JSSPP
1997
Springer
14 years 1 days ago
Memory Usage in the LANL CM-5 Workload
It is generally agreed that memory requirements should be taken into account in the scheduling of parallel jobs. However, so far the work on combined processor and memory schedulin...
Dror G. Feitelson
ASPLOS
2009
ACM
13 years 12 months ago
Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications
As our society becomes more information-driven, we have begun to amass data at an astounding and accelerating rate. At the same time, power concerns have made it difficult to brin...
Adrian M. Caulfield, Laura M. Grupp, Steven Swanso...
EUROMICRO
2009
IEEE
13 years 11 months ago
Synthetic Metrics for Evaluating Runtime Quality of Software Architectures with Complex Tradeoffs
Runtime quality of software, such as availability and throughput, depends on architectural factors and execution environment characteristics (e.g. CPU speed, network latency). Alth...
Anakreon Mentis, Panagiotis Katsaros, Lefteris Ang...
ICCD
2007
IEEE
109views Hardware» more  ICCD 2007»
13 years 11 months ago
Improving cache efficiency via resizing + remapping
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
Subramanian Ramaswamy, Sudhakar Yalamanchili