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» On Variations of Power Iteration
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ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
14 years 4 months ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
JCP
2008
232views more  JCP 2008»
13 years 10 months ago
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper...
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira ...
VTC
2008
IEEE
14 years 4 months ago
Irregular Generic Detection Aided Iterative Downlink SDMA Systems
— When an iterative-decoding aided system is configured to operate at a near-capacity performance, an excessive complexity may be imposed by the iterative process. In this paper...
Chun-Yi Wei, Lajos Hanzo
SIPS
2006
IEEE
14 years 4 months ago
A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold
Although many stopping methods of iterative decoding have been discussed in the literatures extensively, many of them only focus on the solvable decoding. In this paper, we propos...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
ICDT
1997
ACM
138views Database» more  ICDT 1997»
14 years 2 months ago
Tractable Iteration Mechanisms for Bag Languages
Abstract. The goal of this paper is to study tractable iteration mechanisms for bags. The presence of duplicates in bags prevents iteration mechanisms developed in the context of s...
Latha S. Colby, Leonid Libkin