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» On a quasi-ordering on Boolean functions
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ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
13 years 7 months ago
Reduction of interpolants for logic synthesis
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
John D. Backes, Marc D. Riedel
IACR
2011
91views more  IACR 2011»
12 years 8 months ago
A Scalable Method for Constructing Galois NLFSRs with Period $2^n-1$ using Cross-Join Pairs
This paper presents a method for constructing n-stage Galois NLFSRs with period 2n − 1 from n-stage maximum length LFSRs. We introduce nonlinearity into state cycles by adding a ...
Elena Dubrova
STOC
1999
ACM
85views Algorithms» more  STOC 1999»
14 years 1 months ago
A Theorem on Sensitivity and Applications in Private Computation
In this paper we prove a theorem that gives an (almost) tight upper bound on the sensitivity of a multiple-output Boolean function in terms of the sensitivity of its coordinates an...
Anna Gál, Adi Rosén
STOC
2012
ACM
209views Algorithms» more  STOC 2012»
11 years 11 months ago
Nearly optimal solutions for the chow parameters problem and low-weight approximation of halfspaces
The Chow parameters of a Boolean function f : {−1, 1}n → {−1, 1} are its n + 1 degree-0 and degree-1 Fourier coefficients. It has been known since 1961 [Cho61, Tan61] that ...
Anindya De, Ilias Diakonikolas, Vitaly Feldman, Ro...
AHS
2006
IEEE
125views Hardware» more  AHS 2006»
14 years 3 months ago
Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs
Randomly connecting networks have proven to be universal computing machines. By interconnecting a set of nodes in a random way one can model very complicated non-linear dynamic sy...
Andres Upegui, Eduardo Sanchez