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» On computational limitations of neural network architectures
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2009
ACM
14 years 3 months ago
Allocator implementations for network-on-chip routers
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
Daniel U. Becker, William J. Dally
SLIP
2005
ACM
14 years 2 months ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
DSN
2009
IEEE
14 years 20 days ago
Processor reliability enhancement through compiler-directed register file peak temperature reduction
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
Chengmo Yang, Alex Orailoglu
MOBICOM
2009
ACM
14 years 3 months ago
Data fusion improves the coverage of wireless sensor networks
Wireless sensor networks (WSNs) have been increasingly available for critical applications such as security surveillance and environmental monitoring. An important performance mea...
Guoliang Xing, Rui Tan, Benyuan Liu, Jianping Wang...
NSDI
2008
13 years 11 months ago
DieCast: Testing Distributed Systems with an Accurate Scale Model
Large-scale network services can consist of tens of thousands of machines running thousands of unique software configurations spread across hundreds of physical networks. Testing ...
Diwaker Gupta, Kashi Venkatesh Vishwanath, Amin Va...