— In this paper, we propose a fair and simple high-performance scheduling algorithm for Combined Input-Crosspoint-Queued Switches, which is called Tracking Fair Quota Allocation ...
Nan Hua, Peng Wang, Depeng Jin, Lieguang Zeng, Bin...
Evolving semiconductor and circuit technology has greatly increased the pin bandwidth available to a router chip. In the early 90s, routers were limited to 10Gb/s of pin bandwidth...
John Kim, William J. Dally, Brian Towles, Amit K. ...
—This paper presents and evaluates distributed queueing algorithms for regulating the flow of traffic through large, high performance routers. Distributed queueing has a similar ...
Prashanth Pappu, Jyoti Parwatikar, Jonathan S. Tur...
— We consider cell-based switch architectures in which the speedup of the internal switching fabric is not large enough to avoid input buffering. These architectures require a sc...
Emilio Leonardi, Marco Mellia, Marco Ajmone Marsan...
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...