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» On hierarchical statistical static timing analysis
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DAC
2005
ACM
13 years 11 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
DATE
2008
IEEE
204views Hardware» more  DATE 2008»
14 years 4 months ago
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
Jun-Kuei Zeng, Chung-Ping Chen
TVLSI
2008
105views more  TVLSI 2008»
13 years 9 months ago
Fast Estimation of Timing Yield Bounds for Process Variations
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...
Ruiming Chen, Hai Zhou
CSMR
2002
IEEE
14 years 2 months ago
Combining Static and Dynamic Views for Architecture Reconstruction
Static analysis aims at recovering the structure of a software system, while dynamic analysis focuses on its run time behaviour. We propose a technique for combining the analysis ...
Claudio Riva, Jordi Vidal Rodríguez
SERP
2004
13 years 11 months ago
Run-Time Cohesion Metrics: An Empirical Investigation
Cohesion is one of the fundamental measures of the 'goodness' of a software design. The most accepted and widely studied object-oriented cohesion metric is Chidamber and...
Áine Mitchell, James F. Power