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» On modeling top-down VLSI design
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VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 8 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 8 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong
GECCO
2003
Springer
158views Optimization» more  GECCO 2003»
14 years 23 days ago
Active Control of Thermoacoustic Instability in a Model Combustor with Neuromorphic Evolvable Hardware
Continuous Time Recurrent Neural Networks (CTRNNs) have previously been proposed as an enabling paradigm for evolving analog electrical circuits to serve as controllers for physica...
John C. Gallagher, Saranyan Vigraham
DAC
2000
ACM
14 years 8 months ago
GTX: the MARCO GSRC technology extrapolation system
Technology extrapolation -- the calibration and prediction of achievable design in future technology generations ? drives the evolution of VLSI system architectures, design method...
Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farin...
VLSID
2002
IEEE
172views VLSI» more  VLSID 2002»
14 years 8 months ago
Improvement of ASIC Design Processes
With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this con...
Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri