305 search results - page 8 / 61 » On modeling top-down VLSI design |
NIPS
2003
13 years 9 months ago
2003
We have designed and tested a single-chip analog VLSI sensor that detects imminent collisions by measuring radially expansive optic flow. The design of the chip is based on a mode...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
ASPDAC
2005
ACM
14 years 1 months ago
2005
ACM
－ In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
DT
2007
13 years 7 months ago
2007
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...