Sciweavers

1394 search results - page 247 / 279
» On performance limitations of congestion control
Sort
View
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
ESANN
2008
13 years 10 months ago
Learning Inverse Dynamics: a Comparison
While it is well-known that model can enhance the control performance in terms of precision or energy efficiency, the practical application has often been limited by the complexiti...
Duy Nguyen-Tuong, Jan Peters, Matthias Seeger, Ber...
WCE
2007
13 years 9 months ago
Dynamic Traffic Regulation for WiFi Networks
— Multimedia applications require high bandwidth in order to assure certain level of Quality of Service (QoS). It is well known that the characteristics of the traffic for multim...
Domingo Marrero Marrero, Elsa María Mac&iac...
TASE
2008
IEEE
13 years 8 months ago
Randomized Optimal Design of Parallel Manipulators
This work intends to deal with the optimal kinematic synthesis problem of parallel manipulators under a unified framework. Observing that regular (e.g., hyper-rectangular) workspac...
Yunjiang Lou, Guanfeng Liu, Zexiang Li
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 6 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt